A die may be formed of a semiconductor chip overlaid with a number of alternating layers of metallic materials and inter-layer dielectric (ILD) materials. The die may further include passivation materials overlaying the metallic and ILD layers, and one or more layers of insulating material, such as polyimides overlaying the passivation materials.
Typically, solder bumps or other interconnecting structures extending through the layers of insulating material interconnect the die to a substrate, typically formed of an organic material. Collectively, the die and interconnected substrate are typically referred to as an integrated circuit package.
Each of the different materials making up the package has a different coefficient of thermal expansion (CTE). For example, a silicon semiconductor chip may have a CTE of approximately 2.6×10−6/° C.; polyimide may have a CTE of approximately 35×10−6/° C.; lead-free solder material may have a CTE in the range of approximately 20-30×10−6/° C. and an organic substrate may have a CTE of approximately 17×10−6/° C. During manufacture and use, the temperature of the package changes, causing the different materials to expand or contract according to their respective CTE.
CTE mismatches in turn result in thermo-mechanical stress on package components due to differential expansion. Components also tend to warp when subjected to heat, based on CTE differences between the components. This causes peeling stress as components warp away from one another. These stresses are typically referred to as chip package interaction (CPI) stress.
Historically, CPI stress was mitigated, at least in part, by solder bumps interconnecting the die to the substrate. The solder bumps were typically formed from relatively ductile leaded alloys which were capable of deforming in response to differential expansion and warping, thus absorbing stress, and tending to isolate the die and substrate from one another.
Recently, however, leaded solder materials have been replaced with lead-free materials. These lead-free materials tend be stiffer, that is, have lower ductility than leaded materials. As a result, the lead-free solder bumps tend to absorb less stress. In some cases, this can cause cracking or de-lamination of the die from the rest of the package.
This problem is exacerbated by other material choices made necessary by performance requirements. In particular, as semiconductor chip feature sizes decrease, it becomes necessary for performance reasons to select ILD materials having dielectric constant (K) of less than 3 (low-K materials) or less than 2.7 (ultra-low K (ULK) materials). Such materials often have lower shear strength and cohesive strength and poorer adhesion to adjacent die layers than dielectric materials with K>3. Accordingly, low-K and ULK ILD materials are particularly prone to mechanical failure such as cracking or de-lamination.
Accordingly, there is a need for semiconductor package designs which provide improved protection against thermo-mechanical stresses.